As the complexity and scale of circuit integration increases, the amount of capacitance associated with a signal line increases. This is because the capacitance of the signal line increases along with the metal length. As clock speeds increase, the time required for a signal to complete a transition approaches or exceeds the clock period. This becomes problematic in the design of systems where the destinations for the data are scattered from the source of the data.
The term “scattered” as used herein refers to locations where propagation delay from the source to the destination approaches or exceeds the clock period. In general, this occurs either when the signal line is long compared to the clock period or when the capacitance on a signal line is large enough to delay the signal transition. Some examples of such scattered locations are a system with many destinations for the data such as a pad ring on an integrated circuit (IC), a system where the locations exist on multiple IC's, or a system where the locations exist on multiple printed circuit boards. An example of data needing to be distributed to scattered locations throughout a system is data contained in control registers that needs to be distributed to configure the system. Another example is data and control signals for testing the system.
One approach in the design of logic circuitry to distribute data is to use shift registers to distribute data to Flip-Flops or registers residing near the destinations. However, when the destinations are scattered and the data destined for each destination is unique, race conditions can develop where control signals need to reach all of the destinations yet transition fast enough to capture data driven by the fast clock speeds. What is needed is a system and method for ensuring that the control signals arrive at a shift register distributed across the scattered locations before the clock captures the data.